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格罗方德推出四核测试芯片构建Cortex

发布时间:2020-06-29 17:32:09 阅读: 来源:白糖粉碎机厂家

元器件交易网讯 3月21日消息,据外媒报道,Cadence设计系统公司上周称其晶圆合作伙伴格罗方德推出四核测试芯片构建ARM Cortex-A 12处理器。

2GHz处理器可以执行28纳米SLP(超低功率28纳米高介电率金属门)处理。

Cortex-A12处理器比ARM的Cortex-A9智能手机处理器有更高性能。

ARM执行副总裁兼物理设计部门总经理Dipesh Patel表示,28纳米测试芯片使用ARM POP IP意义重大,这将“加速其投放市场的世时间”。

ARM POP技术目的在于实现硬处理器内核,使性能更易预测。ARM公司喜欢称它为“核心硬化”CPU。

它是使用工匠实体IP标准电池、逻辑和内存缓存优化工艺处理技术。

ARM为芯片制造商提供优化平面图、脚本和设计工具,还有详细的性能基准。

(元器件交易网董蕾 译)

外媒原文如下:

Cadence last week announced that foundry partner Globalfoundries had taped out a quad core test chip built around the ARM Cortex-A12 processor.

The 2GHz processor was implemented on a 28nm-SLP (Super Low Power 28 nanometer High-K Metal Gate) process.

The Cortex-A12 processor is the higher performance succssor to ARM"s Cortex-A9 smartphone processor.

According to Dipesh Patel, executive vice president and general manager, physical design group, ARM, it is significant that the 28nm test chip utilised ARM POP IP, this “will accelerate its time to market.”

This is the first POP IP offering for the Cortex-A12.

ARM POP technology is intended to make hard processor core implementation and performance more predictable. The processor firm likes to refer to it as “core hardening” for its CPUs.

The technique invloves the use of Artisan Physical IP standard cells, logic and memory cache optimised for the process technology.

ARM assists the chip fabricator with optimised floor plans, scripts and design utilities. There is also detailed performance benchingmarking to help the foundry.

Cadence"s RTL-to-signoff digital implementation flow was used, including Encounter RTL Compiler, Encounter RTL Compiler with Physical, Encounter Digital Implementation System and Encounter Conformal Equivalence Checker.

“We collaborated closely with Cadence and ARM to implement this new core using our 28nm low-power process, and ARM libraries specifically tuned to meet demanding mobile market requirements,” said Ana Hunter, vice president of product management at Globalfoundries.

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